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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER READ
ted with a BST command, the effective burst length of the truncated burst should be
used for the BL value.
Figure 62: READ to MRR Timing – RL = 3, t MRR = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
BL/2 1
RL = 3
CA[9:0]
Bank m
col addr a
Col addr a
Register
B
Register
B
t MRR
=2
CMD
READ
MRR
NOP 2
Valid
DQS#
DQS
DQ[7:0]
DQ[MAX:8]
D OUT A0
D OUT A0
D OUT A1
D OUT A1
D OUT A2
D OUT A2
D OUT A3
D OUT A3
D OUT B
Transitioning data
Undefined
Notes:
1. The minimum number of clock cycles from the burst READ command to the MRR com-
mand is BL/2.
2. Only the NOP command is supported during t MRR.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
86
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk